Aspects of the present invention are directed to identifying defects in pluralities of wafers by correlating defects to design structure.
In wafer manufacturing processes, in-line inspection tools are used to detect and to report wafer visual defects by comparing wafer images at chip-to-chip locations. Defects are found by inspections performed on each manufactured layer where the wafer images do not match. Reported defects are stored in computer data storage for further analysis. This process is normally referred to interactive defect analysis.
Typically, the number of defects for a specific wafer may count in the hundreds of thousands in early technology development stages. Therefore, interactive defect analysis is prohibitive and automated data analysis is often required. Generally, this type of automated data analysis is aimed at multiple objectives. These include assisting in tuning manufacturing processes to minimize the number of defects, determining physical layout structures that are prone to defects so that learned structures can be incorporated into the design for manufacturing methodologies so that chips become easier to manufacture, determining non-killer defects and providing feedback for tuning the inspection process to minimize oversensitivity and to prevent artifacts from being reported as defects and keeping the analysis algorithm as simple as possible to thereby provide a methodology that is practical from a computational perspective.
With this in mind, existing tools focus mainly on visualizing the defects, and providing basic statistics like defect densities. Some attempt to compare layout shapes of the inspected layer around the defects. This type of analysis is known as pattern matching and has many drawbacks. For example, pattern matching is computationally expensive and forces developers to employ tools using empirical methods (e.g., comparing shape densities or some other easy to calculate properties). Also, orientation independence is hard to solve and is also computationally expensive, high defect coordinate accuracy is required and defects are often caused by interactions between layout structures at multiple layers, such as the inspected layer and the layers below it.